A streaming VHDL image pipeline that uses FIFO line buffers and shift registers to build the 3×3 neighbourhood needed for RGB interpolation.
The problem
Demosaicing needs a local image neighbourhood, but an FPGA camera path receives pixels one after another. The central problem is building that neighbourhood without buffering an entire frame.
What was built
A streaming GBRG Bayer-to-RGB datapath. It accepts one 8-bit input pixel per clock, forms a 3×3 hardware window with line buffers and shift registers, and does the interpolation in RTL.
Technical approach
- Raster-ordered 8-bit Bayer input
- FIFO line buffers keep the previous image rows
- Shift registers assemble the current 3×3 neighbourhood
- Interpolation that is aware of the Bayer phase selects the RGB equations
- Comparison against a Python reference supports functional verification
Engineering decisions
- Use line buffers rather than full-frame storage.
- Keep the datapath streaming at one input pixel per clock.
- Separate neighbourhood construction from colour reconstruction logic.
- Compare hardware output with a software reference before relying on implementation reports.
How it was checked
- Verified against a Python reference implementation.
- Processing of a 1024×1024 image is documented in the repository.
- Timing closure at 100 MHz is documented for the verified target flow.
What it shows
The hardware/software boundary, streaming dataflow, functional comparison against a reference, and implementation-level timing work.
About the source
Academic and engineering R&D. The source repository is private, so no repository link is published.