RTL for FIR signal processing, built around a VHDL datapath, MAC, memory, control logic, testbenches and Vivado implementation.
The problem
Signal-processing hardware needs the arithmetic datapath, control sequencing, coefficient storage and verification environment to agree cycle by cycle.
What was built
FPGA-oriented digital components centred on an FIR datapath: multiply-accumulate logic, RAM/ROM, control units, testbenches and ZYBO-oriented implementation variants.
Technical approach
- Feed samples and coefficients through memory components
- Accumulate products through a MAC datapath
- Coordinate operation with explicit control logic
- Verify behaviour in VHDL testbenches
- Carry the design through Vivado synthesis and implementation files
Engineering decisions
- Split the datapath, memory and control into RTL units that can be tested on their own.
- Hold back resource, frequency and numerical claims until the final implementation has been checked.
- Treat the ZYBO context as verified only where the repository files support it.
How it was checked
- The repository includes fir.vhd, FIR testbenches and ZYBO-oriented variants.
- The VHDL components for the MAC, RAM, ROM and control unit are present.
- Vivado synthesis and implementation files are present.
What it shows
Foundations in digital signal processing and RTL: datapath and control decomposition, memory integration and the implementation workflow.
About the source
Academic and R&D project. Exact implementation measurements are withheld until they have been verified.